The present invention relates to a semiconductor device in which a CMOS logic section and a plurality of DRAM sections used for different applications are formed together on the same semiconductor substrate, and more particularly to a DRAM-embedded system LSI having a reduced power consumption and an increased processing speed while ensuring a sufficient signal holding characteristic.
In recent years, DRAM-embedded system LSI chips have been attracting public attention. In a DRAM-embedded system LSI chip, a CMOS (complementary metal oxide semiconductor) logic section and a general-purpose DRAM (dynamic random access memory) section as a memory device, which used to be formed on separate chips, are formed together on the same chip.
For example, a DRAM-embedded system LSI chip used for an image processing application, or the like, includes a DRAM section as a memory device for storing an image information signal, and a CMOS logic section for retrieving necessary information from the DRAM section and performing an arithmetic operation based on the retrieved information, and the DRAM section and the CMOS logic section are formed together on the same chip.
A DRAM-embedded system LSI chip as described above realizes a higher communication speed than that realized by older techniques where data or information is exchanged between a CMOS logic section and a DRAM section that are formed on separate chips. A semiconductor device in which a CMOS logic section and a plurality of DRAM sections are formed together on the same chip includes a CMOS logic section formed on a silicon substrate, for example, and a DRAM section including cell capacitors (memory cell capacitors) of a particular type formed in the silicon substrate (“trench capacitors”) or on the silicon substrate (“stacked capacitors”).
It was technically difficult to form a CMOS logic section and a DRAM section together on the same chip because they had large areas. However, with recent miniaturization techniques, a DRAM-embedded system LSI chip having a chip size less than or equal to 100 mm2 has been realized. Now, a plurality of CMOS logic sections and a plurality of application-specific DRAM sections are formed on the same chip, whereas a single chip accommodated only one CMOS logic section and one application-specific DRAM section with older techniques.
However, the DRAM sections formed on a conventional DRAM-embedded system LSI chip all have cell capacitors of the same structure. Therefore, it is difficult to provide, on the same chip, a DRAM section that needs to be accessed at a high speed and a DRAM section that requires a sufficient signal holding characteristic. This problem will be further discussed below.
FIG. 12A is a plan view illustrating a general configuration of a conventional DRAM-embedded system LSI chip.
As illustrated in FIG. 12A, a CMOS logic section 11 is formed on a chip 10, and a first DRAM section 12 and a second DRAM section 13 having the same cell capacitor structure are formed on the same chip 10. The first DRAM section 12 is associated with the CMOS logic section 11 and needs to operate at a high speed. On the other hand, the second DRAM section 13 is intended to operate at a low power consumption with a sufficient signal holding characteristic.
The value of a signal stored in each memory cell of a DRAM is determined based on the charge stored in the capacitor of the memory cell. FIG. 12B is a graph illustrating the relationship between the reference charge and the charge stored in a cell capacitor of the first DRAM section 12 and the second DRAM section 13 illustrated in FIG. 12A. Referring to FIG. 12B, where the reference charge, based on which the value of a signal is determined, is set to Qs, the value of a signal stored in a memory cell of the first DRAM section 12 and the second DRAM section 13 is determined to be “high” when a charge Qh, which is larger than the reference charge Qs, is stored in the cell capacitor and to be “low” when a charge Ql, which is smaller than the reference charge Qs, is stored in the cell capacitor.
However, even if the charge Qh is stored in the cell capacitor (whereby the signal stored in the memory cell is supposed to be determined to be “high”), the state of the signal being held may change over time due to, for example, a leak current through the capacitor insulating film of the cell capacitor, an OFF-state leak current through the transfer gate, or a leak current from the substrate contact portion (a portion where the cell capacitor and the semiconductor substrate are connected to each other) to the semiconductor substrate. As a result, even if a charge that is large enough for the signal to be determined “high” is initially stored in a cell capacitor of the DRAM section, the stored charge may gradually leak out over time, whereby the signal of the cell capacitor is no longer determined to be “high”. Where Qh is the charge initially stored in a cell capacitor, t is the charge holding time, which is the amount of time elapsed since the charge Qh is initially stored, Q′ is the amount of charge stored in the cell capacitor after the charge holding time t, and Ileak is the amount of leak current, i.e., the amount of charge that leaks out of the cell capacitor, Q′ can be expressed as in Expression (1) below. For the sake of simplicity, it is assumed that the leak current is constant over time.Q′=Qh−Ileak·t  (1)
As can be seen from Expression (1), the charge stored in the cell capacitor of the DRAM section decreases over time. Therefore, where a sufficient signal holding characteristic is required (i.e., where it is required that the charge holding time t, which is the amount of time until the charge Q′ decreases to be less than or equal to Qs, is long), the charge Qh initially stored in the cell capacitor needs to be increased. Thus, the capacitance of the cell capacitor needs to be as large as about 30 fF.
FIG. 12C is an equivalent circuit diagram illustrating a memory cell of the second DRAM section 13 (the DRAM section that is intended to hold a signal written thereto sufficiently long) illustrated in FIG. 12A. In the figure, “C” denotes a cell capacitor, and “T” denotes a transfer gate. Where the capacitance of the cell capacitor C is set to 30 fF, a charge of 30 fC is stored in the cell capacitor C when a voltage VD applied across the cell capacitor C is set to 1.0 V.
On the other hand, for the first DRAM section 12 (the DRAM section to which signals are written at a high speed), a signal written to a memory cell needs to be transitioned from “low” to “high” and from “high” to “low” at a high speed, whereby the charge stored in the cell capacitor needs to be moved at a high speed. Therefore, a large amount of charge being stored in the cell capacitor means a large amount of charge that needs to be moved at a high speed. Thus, as the capacitance of the cell capacitor is increased, a larger amount of charge will need to be moved, thereby failing to realize a reduced power consumption and an increased processing speed.
Moreover, for devices that are intended for use with portable terminals, or the like, a plurality of DRAM sections formed on the same semiconductor substrate have different operating voltages. For example, the operating voltage of a DRAM section that is required to provide a high processing speed is 2.5 V or 3.3 V, while the operating voltage of a DRAM section that is required to operate at a low power consumption is 1.5 V or 1.2 V. Accordingly, the cell capacitors of these DRAM sections are controlled by the different operating voltages of 2.5 V or 3.3 V and 1.5 V or 1.2 V. If the cell capacitors of the memory cells are of the same structure, a cell capacitor of the DRAM section of the lower operating voltage stores a smaller amount of charge therein. Therefore, the capacitance of the cell capacitor needs to be set so that the amount of charge stored in a cell capacitor of the DRAM section of the lower operating voltage is larger than the reference charge. Thus, the capacitance of the cell capacitors forming the memory cells of the other DRAM section of the higher operating voltage is set equally. Therefore, a cell capacitor of the DRAM section that is controlled by the higher operating voltage stores more charge than necessary, thereby lowering the operating speed and increasing the power consumption.